ElectricMotorcycleForum.com

  • November 26, 2024, 07:29:26 AM
  • Welcome, Guest
Please login or register.

Login with username, password and session length
Advanced search  

News:

Electric Motorcycle Forum is live!

Pages: [1]

Author Topic: New porous silicon battery technology  (Read 304 times)

valnar

  • Sr. Member
  • ****
  • Posts: 365
    • View Profile
New porous silicon battery technology
« on: July 20, 2019, 11:15:49 AM »

While there is no mention of EV use, it's interesting nonetheless.  I'm glad major $$ is going into research.
https://spectrum.ieee.org/energywise/energy/the-smarter-grid/startup-aims-to-tackle-grid-storage-problem-with-serverracksized-battery
Logged
Zero FXS 2020

Mudface

  • Newbie
  • *
  • Posts: 29
    • View Profile
Re: New porous silicon battery technology
« Reply #1 on: July 20, 2019, 05:52:01 PM »

12inch wafers... 4x energy denser.

the Curtis bikes are starting to make sense.
Logged

Fran K

  • Hero Member
  • *****
  • Posts: 637
    • View Profile
Re: New porous silicon battery technology
« Reply #2 on: July 20, 2019, 07:29:47 PM »

"While there is no mention of EV use"

While there is no mention of ev use in the text of the article there are picures of cars, trucks, and airplanes toward the end of the two minute video.

I have to wonder if those shipping container size battery banks they describe need cooling systems not included in the volume.

Why would a company give exclusive rights to distribute to a politician?
Logged

Bill822

  • Full Member
  • ***
  • Posts: 112
    • View Profile
Re: New porous silicon battery technology
« Reply #3 on: July 21, 2019, 08:57:18 AM »

I don't get the economics of this. Etching silicon wafers is costly.
"The minimum silicon cost reached with 300mm [12"] diameter wafers is about $3 per square inch, resulting in a maximum cost per wafer to of $400."
And that's before plating, packaging, etc. How can this possibly be cost effective?

source: https://www.semi.org/en/macroeconomics-450mm-wafers
Logged

Curt

  • Hero Member
  • *****
  • Posts: 670
    • View Profile
Re: New porous silicon battery technology
« Reply #4 on: July 22, 2019, 01:46:07 PM »

They're talking about wafers with a feature size of 20 microns, which was the state of the art for integrated circuits in 1970, and the silicon might not need to be very pure. So it might be possible to produce such wafers cheaply.

But yeah, if a small company was able to afford exclusive license rights, then maybe it's not that promising.
Logged
Pages: [1]